Generally, integrated circuits are mass produced by forming many identical circuit patterns on a single silicon wafer. Integrated circuits, also commonly referred to as semiconductor devices, are made of various materials that may be electrically conductive, electrically nonconductive (insulators) or electrically semiconductive. Silicon, in single crystal or polycrystalline form, is the most commonly used semiconductor material. Both forms of silicon can be made electrically conductive by adding impurities, commonly referred to as doping. Silicon is typically doped with boron or phosphorus. If the silicon is doped with boron, which has one less valance electron than silicon, electron "holes" become the dominant charge carrier and the doped silicon is referred to as P-type silicon. If the silicon is doped with phosphorous, which has one more valance electron than silicon, electrons become the dominant charge carriers and the doped silicon is referred to as N-type silicon.
DRAMs comprise arrays of memory cells which contain two basic components--a field effect access transistor and a capacitor. Typically, one side of the transistor is connected to one side of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other side of the capacitor is connected to a reference voltage. Therefore, the formation of the DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
It is advantageous to form integrated circuits with smaller individual elements so that as many elements as possible may be formed in a single chip. In this way, electronic equipment becomes smaller and more reliable, assembly and packaging costs are minimized and circuit performance is improved. The capacitor is usually the largest element of the integrated circuit chip. Consequently, the development of smaller DRAMs focuses in large part on the capacitor. Three basic types of capacitors are used in DRAMs--planar capacitors, trench capacitors and stacked capacitors. Most large capacity DRAMs use stacked capacitors because of their greater capacitance, reliability and ease of formation. For stacked capacitors, the side of the capacitor connected to the transistor is commonly referred to as the "storage node" or "storage poly" and the side of the capacitor connected to the reference voltage is called the "cell poly."
The areas in a DRAM to which electrical connections are made are generally referred to as active areas. Active areas, which serve as source and drain regions for transistors, consist of discrete specially doped regions in the surface of the silicon substrate. As the size of the DRAM is reduced, the size of the active areas and the corridors available for contacts to reach the active areas are also reduced. The chances for leakage or short circuits between the contacts and transistor and capacitor components increases as the cell spacing decreases. Hence, it is desirable to effectively isolate the contacts from the transistor and capacitor components while optimizing the space available to make the contacts. The present invention addresses the problems associated with forming the contact between the bit line and an active area in the substrate, properly aligning this "bit line contact" and isolating it from the capacitor components.
One method of forming bit line contacts is disclosed in U.S. Pat. No. 5,292,677, issued to Dennison on Mar. 8, 1994. Dennison describes a DRAM formation process using an etch stop layer to self-align the bit line contact to the transistor gate electrode. Although this method requires fewer mask steps than other methods, it requires forming and etching insulating spacers in the bit line contact corridor.
Another method of forming a bit line contact is disclosed in Two-Step Deposited Rugged Surface (TDRS) Storage Node and Self-Aligned Bitline-Contact Penetrating Cell Plate (SAB-PEC) for 64 Mb DRAM STC Cell by H. Itoh et al. in IEEE 1991 Symposium on VLSI Technology, pp. 9-10. This process utilizes a bit line contact that passes through the cell poly. To insulate the bit line from the cell poly, sidewall spacers are formed between the transistor gate electrodes. These spacers narrow the corridor for the bit line contact and, consequently, require the use of a poly-silicide bit line since metal would not properly fill the narrow corridor. For very small cell spacing, as in a 64 Mbit DRAM, the bit line corridor would be completely closed off if the cell poly spacer is greater than 0.1 .mu.m. Such thin spacers are difficult to form and may result in an unacceptably large number of devices with cell poly to bit line current leakage.